Low Jitter Phase-Locked Loop

For high speed application, jitter is a problem to communication system, as it reduces the performance of overall circuitry. As jitter is a type of corruption that cannot be eliminated, reducing jitter is one way to help to improve the system performance. In this paper, we introduce some ways to reduce the jitter in phase-locked loop. Introduction Phase-Locked Loop, PLL, is widely used among the electronics and communication systems, for clock and data recovery, frequency synthesis, clock synchronization in microprocessors, and many applications. In high speed application, Gbit/s range, data rates increase, data eye opening becomes narrower. The received data and clock therefore become more susceptible to various noise sources, of which supply and substrate noise are the most dominant. It is important, therefore, to design a low jitter PLL, that is highly tolerant of supply and substrate noise, enabling jitter reduction. Signals often experience timing jitter as they travel through a communication channel or as they are retrieved from a storage medium. Jitter manifests itself as variation of the period of a waveform, a type of corruption that cannot be removed by amplification and clipping [1]. While jitter represents the time-domain description, phase noise is the corresponding frequency-domain equivalent of the same physical effect. In typical applications, jitter requirements range from on the order of 100 picoseconds r.m.s. down to less than 5 picoseconds in very high speed communications receivers, for instance. Jitter can arise from many sources, including noise from other parts of the circuit through the power supply. This kind of noise can often be minimized by the use of differential circuit technique, shown in previous research. In this paper, we discuss the methods to reduce the jitter in PLL. Since VCO is the major source of jitter in the PLL system, we will show some new ways to minimize the jitter in VCO. The new layout technique for VCO and circuits for reducing jitter are presented in the following sections. Background Basic Topology of Phase-Locked Loop PLL simply consists of a phase detector (PD), low-pass filter (LPF), and voltagecontrolled oscillator (VCO) in a feedback loop, Fig. 1. The PD compares the phases of Vout and Vin, generating an error signal that varies the VCO frequency until the phases are aligned, that is the loop is locked. The low-pass filter is used to extract the average value from the output of the phase detector. This average value is used to drive the VCO. The output of the VCO is synchronized with the input signal, by the negative feedback loop. Fig. 1 Basic architecture of a phase-locked loop. PD LPF VCO VPD Vcont Vou Φout Φin Vin A) Phase detector (PD) The phase detector compare the phase of input signal and output of VCO, and generate an average output , which is linearly proportional to the phase difference, ∆Φ, between its two inputs. In the ideal case, the relationship between and ∆Φ, is linear, crossing the origin for ∆Φ = 0. [3] The simplest example of phase detector is an exclusive OR, XOR gate. The width of the output pulses varies with the phase difference between the inputs that providing a dc level proportional to ∆Φ. The error pulses on both rising and falling edges can be produced by the XOR circuit, but other types of PD only respond to positive or negative transitions. B) Voltage-controlled oscillator (VCO) Voltage-controlled oscillator (VCO) is simply an oscillator whose frequency is proportional to a control voltage, Vcont, with a function: where ωFR is the “free-running” frequency and KVCO is the “gain” of the VCO (rad/s/V). The output of a sinusoidal VCO can be expressed as so the phase is the time integral of frequency. In practical VCOs, Kvco exhibits some dependence on the control voltage and eventually drops to zero as Vcont increases. If Vcont(t) = Vm cos ωmt, then Vout cont VCO FR out V K + = ω ω ) cos( ) ( dt V K t A t y t cont VCO FR ∫ ∞ − + = ω ) sin cos( ) ( t V K t A t y m m m VCO FR ω ω ω + = ∫ = Φ dt V K t cont VCO out ) (